應(yīng)屆畢業(yè)生
學(xué)歷不限
2025-01-24 20:58:13
2188人關(guān)注
職位描述
該職位還未進行加V認(rèn)證，請仔細(xì)了解后再進行投遞！
職責(zé)描述:
1.RTL synthesis, SDC/UPF verification, low power design implementation for advanced technology chips.
2.Design flow/methodology development and innovation for front-end design challenges.
3.Be responsible for RTL verification, synthesis, low power design, and STA/timing closure works for customer’s projects and internal system test chips.
任職要求:
1.MS or above in EE, CS related fields. Experience in Digital IC design flow (from Synthesis, DFT, MBIST, Formality, STA), RTL design, RTL verification is plus.
2.New graduate or 3 years working experience.
3.Familiar with EE CAD tool such as Design compiler, DFT complier, MBIST, n-Lint, Verdi, Verilog tools/flows.
4.Familiar with tcl/Perl/Python program.
招聘人數(shù)：1人
注：聯(lián)系我時，請說是在江南人才網(wǎng)上看到的。
工作地點
地址：南京江寧區(qū)南京-江寧區(qū)九龍湖
求職提示：用人單位發(fā)布虛假招聘信息，或以任何名義向求職者收取財物（如體檢費、置裝費、押金、服裝費、培訓(xùn)費、身份證、畢業(yè)證等），均涉嫌違法，請求職者務(wù)必提高警惕。
職位發(fā)布者
HR
臺積電(南京)有限公司
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電子技術(shù)·半導(dǎo)體·集成電路
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200-499人
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外商獨資·外企辦事處
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浦口經(jīng)濟開發(fā)區(qū)紫峰路16號
